1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to an improvement for preventing the semiconductor device from destruction during a turn-off state.
2. Description of the Background Art
FIG. 5 is a perspective sectional view showing the structure of a conventional power diode. In this device 100, an N.sup.+ layer 4 is formed on the lower major surface of a semiconductor substrate (semiconductor body) 10 into which an N-type impurity is introduced in low concentration by diffusing an N-type impurity in high concentration, while a P-type diffusion layer 2 is selectively formed on a central portion of the upper major surface by selectively diffusing a P-type impurity. Annular P-type diffusion layers 3, for example, are selectively formed in the peripheral portion of the P-type diffusion layer 2 in the upper major surface, to enclose the P-type diffusion layer 2. Namely, the semiconductor substrate 10 has the N.sup.+ layer 4, the P-type diffusion layer 2, the P-type diffusion layers 3, and an N.sup.- layer 1 which is a region excluding these layers.
Further, an anode electrode 5 is in ohmic contact with an exposed surface of the P-type diffusion layer 2, while a cathode electrode 6 is in ohmic contact with an exposed surface of the opposite N.sup.+ layer 4. Namely, the anode electrode 5 and the cathode electrode 6 are formed on opposite major surfaces to hold the semiconductor substrate 10.
The P-type diffusion layer 2 is not formed on the overall upper major surface of the semiconductor substrate 10 but is only selectively formed on a partial region, in order to ensure strength against a reverse voltage, i.e., blocking voltage. The blocking voltage is increased as the width L of the peripheral portion of the P-type diffusion layer 2 is increased. The blocking voltage is further improved by providing the annular P-type diffusion layers 3 in the peripheral portion of the P-type diffusion layer 2.
The N.sup.+ layer 4 is adapted to prevent a depletion layer from reaching the cathode electrode 6 upon application of a reverse voltage while thinning the semiconductor substrate 10 and suppressing forward voltage drop, thereby attaining high blocking voltage. The width L of the peripheral portion and the thickness D of the semiconductor substrate 10 are set in the range of L.gtoreq.D in general.
This device 100 operates as follows. When a forward voltage is applied across the anode electrode 5 and the cathode electrode 6, holes are injected from the P-type diffusion layer 2 into the N.sup.- layer 1, while electrons are injected from the N.sup.+ layer 4 into the N.sup.- layer 1. Consequently, a forward current flows from the anode electrode 5 to the cathode electrode 6. Namely, the device 100 conducts.
When the forward voltage which is applied across the anode electrode 5 and the cathode electrode 6 is reversed to a reverse voltage, i.e., when the device 100 is turned off, a reverse current transiently flows from the cathode electrode 6 to the anode electrode 5 until the electrons and the holes which are stored in the N.sup.- layer 1 are collected in the N.sup.+ layer 4 and the P-type diffusion layer 2 respectively. Namely, the device 100 continues its conducting state until the carriers stored in the N.sup.- layer 1 disappear, and enters a cutoff state after the disappearance of the stored carriers.
As hereinabove described, the device 100 conducts when a forward voltage is applied thereto, while the same is cut off after a lapse of a constant transient time when a reverse voltage is applied thereto. Namely, the device 100 serves as a diode.
In the conventional device 100, the P-type diffusion layer 2 is selectively formed on the upper major surface of the semiconductor substrate 10 and the width L of the peripheral portion is set to be in excess of a constant size in order to ensure blocking voltage, as hereinabove described. On the other hand, the cathode electrode 6 is formed to cover the overall lower major surface of the semiconductor substrate 10.
When a forward voltage is applied to the device 100, therefore, an electric field generated in the semiconductor substrate 10 spreads not only in a region immediately under the P-type diffusion layer 2 but to a peripheral region 13 which is an outer region thereof, as typically shown by arrows in a front sectional view of FIG. 6. Consequently, the carriers which are injected from the P-type diffusion layer 2 and the N.sup.+ layer 4 into the N.sup.- layer 1 spread also to the peripheral region 13. Namely, the carriers are widely stored also in the peripheral region 13 outside the region immediately under the P-type diffusion layer 2.
When the device 100 is turned off, therefore, the carriers which are also widely stored in the peripheral region 13 of the semiconductor substrate 10 rush to a peripheral edge portion 7 of the P-type diffusion layer 2. Namely, a reverse current flows in the peripheral edge portion 7 in high density. Consequently, the device 100 is easy to be destructed during a turn-off state under high speed switching.